Allowing Software Developers to Debug HLS Hardware
نویسندگان
چکیده
High-Level Synthesis (HLS) is emerging as a mainstream design methodology, allowing software designers to enjoy the benefits of a hardware implementation. Significant work has led to effective compilers that produce high-quality hardware designs from software specifications. However, in order to fully benefit from the promise of HLS, a complete ecosystem that provides the ability to analyze, debug, and optimize designs is essential. This ecosystem has to be accessible to software designers. This is challenging, since software developers view their designs very differently than how they are physically implemented on-chip. Rather than individual sequential lines of code, the implementation consists of gates operating in parallel across multiple clock cycles. In this paper, we report on our efforts to create an ecosystem that allows software designers to debug HLSgenerated circuits in a familiar manner. We have implemented our ideas in a debug framework that will be included in the next release of the popular LegUp high-level synthesis tool.
منابع مشابه
CHO: A Benchmark Suite for OpenCL-based FPGA Accelerators
Programming FPGAs with OpenCL-based high-level synthesis frameworks is gaining attention with a number of commercial and research frameworks announced. However, there are no benchmarks for evaluating these frameworks. To this end, we present CHO benchmark suite an extension of CHStone, a commonly used C-based high-level synthesis benchmark suite, for OpenCL. We characterise CHO at various level...
متن کاملHigh-Level Synthesis of In-Circuit Assertions for Verification, Debugging, and Timing Analysis
Despite significant performance and power advantages compared to microprocessors, widespread usage of FPGAs has been limited by increased design complexity. High-level synthesis (HLS) tools have reduced design complexity but provide limited support for verification, debugging, and timing analysis. Such tools generally rely on inaccurate software simulation or lengthy registertransfer-level simu...
متن کاملEnabling FPGAs for the Masses
Implementing an application on a FPGA remains a difficult, non-intuitive task that often requires hardware design expertise in a hardware description language (HDL). High-level synthesis (HLS) raises the design abstraction from HDL to languages such as C/C++/Scala/Java. Despite this, in order to get a good quality of result (QoR), a designer must carefully craft the HLS code. In other words, HL...
متن کاملA Comparison of High Level Synthesis and Register Transfer Level Design Techniques for Custom Computing Machines
The most expensive component in the process of building a Custom Computing Machine is the time consuming and highly qualified work of hardware designers. This hinders the wide proliferation of CCMs and pushes this innovative technology into a niche market of research applications. To widen the range of potential applications, the large community of software developers must be attracted. A poten...
متن کاملGuest Editors' Introduction: Raising the Abstraction Level of Hardware Design
DESIGN COMPLEXITY is continually rising with the higher levels of integration implied by Moore’s law. Functional complexity increases with our ability to incorporate more computation in SoCs and to create more complex applications. Additional complexity is also introduced in the design process by the need to control power consumption and to tackle challenges with respect to physical timing clos...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
- CoRR
دوره abs/1508.06805 شماره
صفحات -
تاریخ انتشار 2015